Chip design and subsequent mask pattern generation is a time consuming and costly operation. In an electron beam (e-beam) mask writing system using a shaped beam lithography system for a chip design involving a large number of dense circuits, it is not unusual for the number of shots to make up the complete pattern to be in the order of 1E10 shots or more.
A brief summary of what typically occurs in the design process is as follows. The chip designer produces design data for each mask level. The design data is checked for errors. Then optical proximity correction (OPC) and rules checking is performed on the data and the data modified accordingly. This data is sent to mask fabrication where the data is post-processed to provide pattern generation data for the exposure tool type to be used in the mask making process. Finally, using this data, a mask is created for each chip design layer.
In the above process, the OPC and other compensation techniques used take the original shape design data and modify the data, such as by adding dimensions to selected shapes in one or more areas, to compensate for effects such as those due to the lithographic process, the chip production process and pattern densities.
It is not uncommon for the mask patterns thusly generated to create one or more images that violate physical ground rules for the chip created from the mask. For that reason, following initial mask exposure, the exposure is inspected for such problems. Any defects found would then be identified and reported back to the chip designer. The chip designer would then attempt to correct the design data and the whole process would be repeated, causing a significant additional expense in time and effort.